In electronic devices a supply voltage must be provided to supply power for the associated electronic circuitry to operate. Transients or other types of noise on the supply voltage can result in improper operation of the electronic circuitry. Noise can result from a variety of different sources, such as adjacent electronic circuitry, high power electronic devices where relatively high currents are being switched, or electrostatic discharge (“ESD”) events. Regardless of the source of the noise, the noise can introduce transients on the supply voltage of the electronic circuitry that causes improper operation of the electronic circuitry. To prevent such transients from adversely affecting the operation of the electronic circuitry, decoupling capacitors are connected between ground and a supply voltage source that provides the supply voltage. In this way, the decoupling capacitors function as filters to reduce or eliminate spurious transients on the supply voltage which may adversely affect the operation of the electronic circuitry.
In the past, decoupling capacitors were discreet components positioned adjacent to an integrated circuit package (chip) mounted on a printed circuit board, with each decoupling capacitor being positioned adjacent a respective chip. Multiple decoupling capacitors could be positioned adjacent a single chip. The decoupling capacitors were coupled across conductive traces on the printed circuit board supplying ground and the supply voltages to the corresponding chip. These external decoupling capacitors occupied valuable space on the printed circuit board, introduced unwanted inductance in the path of the supply voltage, and required additional manufacturing operations to position and connect the capacitors to the printer circuit board.
Today, decoupling capacitors are commonly fabricated on a semiconductor die along with other electronic components forming the electronic circuitry contained in a given chip. Each chip includes a package that houses the semiconductor die. Because the semiconductor die is contained within the package and since the decoupling capacitors are formed on the die, this type of decoupling capacitor is termed an internal decoupling capacitor in that the capacitors are contained inside the package of the chip. The internal location of the decoupling capacitors helps minimize the effects of ESD events or other transients and noise on the supply voltage that can damage the electronic circuitry of the chip, as will be appreciated by those skilled in the art.
When fabricating internal decoupling capacitors on a semiconductor die, there are typically a relatively large number of such internal decoupling capacitors on each die. As a result, as with all components being formed on a semiconductor die, there is a probability that some of these internal decoupling capacitors will be defective. For example, the internal decoupling capacitors are typically formed using an oxide layer that is formed on the semiconductor die for use in constructing other electronic components contained on the semiconductor die, such as a gate oxide layer for forming metal-oxide-semiconductor (“MOS”) transistors. The decoupling capacitors are formed by constructing two conductive plates separated by this oxide layer, which functions as the dielectric of each decoupling capacitor. The oxide layer may be unevenly formed and thus thinner in some regions than in others. If a decoupling capacitor is formed utilizing the oxide of such a thin region, the capacitor may be defective since the undesirably thin oxide may result in a short circuit between the conductive plates of the capacitor. Such a defective capacitor results in an undesirable consumption of power since the defective capacitor presents a short circuit between the supply voltage and ground for the corresponding chip.
If the defective capacitors were to remain connected to the power supply, then the corresponding chip may consume an undesirably high amount of power. This could result in the failure or turning off of a power supply providing power to the chip due to excessive current draw from the power supply. Even where the excess current does not result in the power supply failing or turning off, it could result in an undesirable reduction in the supply voltage that could cause chips on the printed circuit board to operate improperly. Either situation is obviously undesirable, with the turning off or shutting down of the power supply rendering electronic circuitry including the chip unusable and a lower power supply voltage similarly being undesirable since such a lower voltage could compromise the proper operation of the chip, as will be appreciated by those skilled in the art.
Due to these problems presented by defective decoupling capacitors, various prior approaches have been utilized to prevent such defective decoupling capacitors from adversely affecting the operation of the chip and associated components connected to the same power supply. FIG. 1 is a schematic of a conventional fused decoupling capacitor control circuit 100 utilized to prevent a defective internal decoupling capacitor 102 from adversely affecting the operation of an associated chip (not shown) containing the decoupling capacitor. The decoupling capacitor 102 is coupled in series with a fuse 104 between a supply voltage plane that receives a supply voltage Vdd and a reference voltage plane that is coupled to ground. When the decoupling capacitor 102 is not defective, the capacitor and fuse 104 are connected in series between the supply voltage Vdd and ground and the capacitor performs the desired decoupling function and suppresses ESD and noise transients on the supply voltage plane.
When the decoupling capacitor 102 is defective, excessive current flows through the capacitor and fuse 104, resulting in the fuse blowing or opening to thereby isolate the capacitor from the supply voltage Vdd and eliminate current flow through the capacitor. Note that when the decoupling capacitor 102 is defective this defective capacitor is completely and permanently removed from operation in the control circuit 100. This reduces the overall decoupling capacitance of the associated chip, which corresponds to the sum of all the decoupling capacitors 102 coupled in parallel. If enough decoupling capacitors 102 are defective, the overall decoupling capacitance can be reduced to the point that the overall decoupling capacitance no longer adequately protects the chip from, for example, ESD events. More specifically, ESD events may result in transients on the supply voltage such that the reduced overall decoupling capacitance due to defective capacitors 102 may result in inadequate suppression of such transients and thereby result in damage to the associated chip due to the transients.
FIG. 2 is a schematic illustrating a conventional current-limited decoupling capacitor control circuit 200 utilized to prevent a defective internal decoupling capacitor 202 from adversely affecting the operation of an associated chip (not shown). The decoupling capacitor 202 and an NMOS transistor 204 are connected in series between a supply voltage plane that receives a supply voltage Vdd and reference voltage plane that is coupled to ground. When the capacitor 202 is functioning properly, the supply voltage Vdd is applied to the gate of the transistor 204, turning ON the transistor hard so that one terminal of the capacitor 202 is coupled to ground through the transistor. In this way the decoupling capacitor 202 is effectively coupled between the supply voltage Vdd and ground to perform the desired decoupling function. Note that in the present description various components may be said to be coupled to the supply voltage Vdd or ground for ease of description, with one skilled in the art understanding that the component is actually being coupled to the supply voltage plane or reference voltage plane.
When the capacitor 202 is defective, however, the transistor 204 functions like a diode-coupled transistor (i.e., drain coupled to gate via defective decoupling capacitor) to thereby limit the current that flows through the defective decoupling capacitor, with the transistor being sized to limit the current to a desired value. With the current-limited decoupling capacitor control circuit 200, note that the defective decoupling capacitor 202 remains actively connected. This is true because if an ESD event causes a transient on the supply voltage Vdd that increases the value of the voltage on the supply voltage plane, for example, the transistor 204 and defective capacitor 202 allow current to flow through these series-connected components to ground to thereby function to suppress the ESD transient. Moreover, a higher voltage on the supply voltage plane from such a transient results in the transistor 204 turning ON harder, which allows more current flow through the capacitor 202 and transistor 204 to better suppress the transient.
FIG. 3 is a schematic illustrating a conventional active-control decoupling capacitor control circuit 300 utilized to prevent a defective internal decoupling capacitor 302 from adversely affecting the operation of the associated chip (not shown). The active-control decoupling capacitor control circuit 300 includes a decoupling capacitor 302 and an NMOS transistor 304 connected in series between a supply voltage plane that receives a supply voltage Vdd and a reference plane coupled to ground. The control circuit 300 further includes an inverter 306 having its input coupled to the drain of the transistor 304 and its output coupled to the gate of the transistor. A resistor 308 is connected between the input of the inverter and ground to assure that transistor 304 will be turned ON when capacitor 302 is functioning properly.
In operation, when the capacitor 302 is functioning properly the inverter 306 drives its output high, turning ON the transistor 304 and thereby coupling the capacitor 302 between the supply voltage Vdd and ground. The capacitor 302 is at this point coupled to perform its desired decoupling function and suppress ESD and other transients on the supply voltage plane. When the capacitor 302 is defective, however, the voltage at the drain of the transistor 304 increases towards the supply voltage Vdd. When this voltage at the drain exceeds a threshold of the inverter 306, the inverter drives its output low, which turns OFF the transistor 304 and thereby isolates the capacitor 302 from ground to remove the defective capacitor from the circuit.
With the control circuit 300, when the capacitor 302 is functioning properly (i.e., is not defective) an ESD event could trip the inverter 306 such that the inverter drives its output low and thereby turns OFF the transistor 304, even though the capacitor is not defective. This is true because an ESD transient on the supply voltage plane could be bootstrapped through the capacitor 302 to the input of the inverter 306, causing the inverter to drive its output low and thereby turning OFF the transistor 304 as just described. The resistor 308 limits the voltage at the output of the inverter 306 and prevents a large bootstrapped voltage from being developed at the output of the inverter responsive to the bootstrapped voltage at the input of the inverter, which could damage the transistor 304.
Even after the ESD transient has dissipated the inverter 306 can remain turned OFF until the voltage at its input drops below a threshold or trip value of the inverter. The node formed by the interconnection of the drain of transistor 304, input of inverter 306, and one terminal of the capacitor 302 is a capacitive node that will take a finite time to discharge. The time it takes the voltage on this node and thus the voltage at the input of the inverter 306 to reach the threshold value determines how long the capacitor 302 is effectively removed from the circuit and not performing the desired decoupling function. The circuit 300 may undesirably remove good decoupling capacitors 302 from the circuit responsive to an ESD transient, meaning that if a subsequent transient is received while some decoupling capacitors are removed the overall decoupling capacitance of the associated chip is less than its desired value. This reduced overall decoupling capacitance means the magnitude of an ESD transient voltage on the supply voltage plane will have a larger value than if all good decoupling capacitors 302 were properly connected, which could damage circuitry in the chip.
FIG. 3A is a schematic illustrating another conventional active-control decoupling capacitor control circuit 300A utilized to prevent a defective internal decoupling capacitor 302A from adversely affecting the operation of the associated chip (not shown). The circuit 300A is similar to the circuit 300 of FIG. 3 and thus similar components have been given the same reference numbers followed by the designation “A” in FIG. 3A. In the control circuit 300A, a resistor 308A is coupled between the supply voltage plane and the gate of the transistor 304A, in contrast to the resistor 308 of FIG. 3. In operation, when the decoupling capacitor 302A is not defective, the inverter 306A drives its output high, turning ON the transistor 304A and coupling the capacitor 302A between the supply voltage Vdd and ground to provide the desired decoupling function.
When the decoupling capacitor 302A is defective, the voltage at the input to the inverter 306A is sufficiently high to trip the inverter, causing the inverter to drive its output low and thereby turning OFF transistor 304A. A resistor 308A is provided to assure that under steady state conditions with a good capacitor 302A that transistor 304A is turned ON. In practice, however, even though a transient from an ESD event will be transmitted to the gate of the transistor 304A via the resistor 308A this transient may not be sufficient to turn ON the transistor. This is true because the resistor 308A has a relatively high value to limit the voltage at the gate of the transistor 304A and prevent the transistor from being damaged by a transient.
There is a need for a decoupling capacitor control circuit and method that provides reliable operation when the associated decoupling capacitor is defective and functioning properly.